DLL circuits are utilized in a broad range of applications that include microprocessors, memory devices (DRAM), and clock and data recovery in a communication system. Clock generation using DLL circuits has been an essential design building block in IC systems. The quality of multiphase clock signals generated by DLL circuits plays an important role and directly determines the performance of a system. In particular, in today's IC applications, the technology trend of higher frequency and faster data processing rate results in using both rising and falling clock edges, which necessitates high quality clock signals. Furthermore, a system may operate simultaneously using multiple clock phases (i.e., multiple clock signals having the same period but different phases), which imposes a strict requirement on the duty cycle of the various delay clock signals. In general, a system operating with clock signals having 50% duty cycles supports wider timing margin and hence better system performance and better tolerance to temperature and semiconductor process variation than a system having clock signals that do not have a 50% duty cycle.
FIG. 12 is a simplified diagram showing a conventional DLL circuit 50, which includes a serial connection of delay cells 51 to 54, a phase detector 56, a charge pump 58, and loop filter 59.
Each delay cell 51 to 54 includes a delay buffer DLY and a bias circuit 55, and generates an associated delayed clock signal CK1 to CKN. A Reference Clock signal having a reference clock cycle (TPERIOD) is applied to an input terminal of the delay buffer DLY of initial delay cell 51 and to a first input terminal of phase detector 56. The delay buffer DLY of initial delay cell 51 generates a first delayed clock signal CK1 having a phase that differs from the applied Reference Clock signal by a first delay amount that is determined by an operating state of associated delay circuit 55. Second delay cell 52 receives first delayed clock signal CK1, and generates a second delayed clock signal CK2 having a phase that differs from the applied Reference Clock signal by a second delay amount, which is ideally two times the first delay amount. Similarly, third delay cell 53 receives second delayed clock signal CK2, and generates a third delayed clock signal CK3 that phase that differs from the applied Reference Clock signal by a third (i.e., 3×) delay amount. Finally, a last delay cell 54 generates an Nth delayed clock signal CKN that is applied to a second input terminal of phase detector 56.
Phase detector 56, charge pump 58, and loop filter 59 cooperate to control the delay periods t1 to tN of delay cells 51 to 54 such that the Nth delayed clock signal CKN is synchronized to (i.e., in phase with) the Reference Clock signal. Phase detector 56 generates output signals (e.g., UP and DOWN) that are used to control charge pump 58, which cooperates with loop filter 59 to generate a feedback control signal Vcnt1 that is used to control bias circuits 55 of each of the delay cells 51 to 54. When conventional DLL circuit 50 is in an ideal lock condition, clock signals CK1 to CKN are distributed uniformly in one period of a reference clock cycle (TPERIOD) due to the substantially identical delay cells 51 to 54. That is, because of the feedback loop, the fundamental constraint on conventional DLL circuit 50 is that a sum of the delays contributed from each delay cell 51 to 54 has to be equal to TPERIOD (i.e., t1+t2+t3+ . . . +tN=TPERIOD; where N is the total number of delay units).
A problem associated with conventional DLL circuit 50 is that there are no constrains on the duty cycle of each clock signal CK1 to CKN. Due to parasitic loading of each stage (i.e., each delay cell), the waveform and duty cycle of clock signals CK1 to CKN are progressively degraded through the delay chain. As a result, conventional DLL circuit 50 is not able to guarantee the quality of clock signals CK1 to CKN because it lacks physical architecture and circuit constraints needed to produce high quality clock waveforms having a 50% duty cycle. Mathematically, the architecture of a conventional DLL establishes only one constraint equation (i.e., t1+t2+t3+ . . . +tN=TPERIOD), and there is no guarantee that the phases are uniform (i.e., t1=t2=t3 . . . =tN). As clock frequencies reach the GHz (gigahertz) range and above, conventional DLL circuit 50 becomes more difficult to operate due to inherent process mismatch and parasitic loading imposed on the semiconductor device during manufacture.
What is needed is a DLL circuit that overcomes the duty cycle offset problems associated with conventional DLL circuits, and generates consistent multiphase clock signals regardless of fabrication process variations.